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1/49 june 2003 m29dw324dt m29dw324db 32 mbit (4mb x8 or 2mb x16, dual bank 16:16, boot block) 3v supply flash memory features summary n supply voltage Cv cc = 2.7v to 3.6v for program, erase and read Cv pp =12v for fast program (optional) n access time: 70, 90ns n programming time C 10s per byte/word typical C double word/ quadruple byte program n memory blocks C dual bank memory array: 16mbit+16mbit C parameter blocks (top or bottom location) n dual operations C read in one bank while program or erase in other n erase suspend and resume modes C read and program another block during erase suspend n unlock bypass program command C faster production/batch programming n v pp /wp pin for fast program and write protect n temporary block unprotection mode n common flash interface C 64 bit security code n extended memory block C extra block used as security block or to store additional information n low power consumption C standby and automatic standby n 100,000 program/erase cycles per block n electronic signature C manufacturer code: 0020h C top device code m29dw324dt: 225ch C bottom device code m29dw324db: 225dh figure 1. packages tsop48 (n) 12 x 20mm fbga tfbga63 (za) 7 x 11mm fbga tfbga48 (ze) 6 x 8mm
m29dw324dt, m29dw324db 2/49 table of contents summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 3. tsop connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 4. tfbga63 connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 5. tfbga48 connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 2. bank architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 6. block addresses (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 7. block addresses (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 address inputs (a0-a20). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 data inputs/outputs (dq0-dq7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 data inputs/outputs (dq8-dq14). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 data input/output or address input (dq15aC1).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 chip enable (e). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 output enable (g). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 write enable (w). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 v pp/ write protect (v pp/ wp). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 reset/block temporary unprotect (rp). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 ready/busy output (rb). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 byte/word organization select (byte). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 v cc supply voltage (2.7v to 3.6v).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 v ss ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 bus operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 bus read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 bus write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 output disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 automatic standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 special bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 electronic signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 block protect and chip unprotect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 block protect and chip unprotect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 3. bus operations, byte = v il . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 4. bus operations, byte = v ih . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 read/reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 auto select command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 fast program commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3/49 m29dw324dt, m29dw324db quadruple byte program command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 double word program command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 unlock bypass command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 unlock bypass program command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 unlock bypass reset command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 chip erase command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 block erase command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 erase suspend command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 erase resume command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 enter extended block command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 exit extended block command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 5. commands, 16-bit mode, byte = v ih . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 6. commands, 8-bit mode, byte = v il . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 7. program, erase times and program, erase endurance cycles . . . . . . . . . . . . . . . . . . . . 19 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 data polling bit (dq7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 toggle bit (dq6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 error bit (dq5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 erase timer bit (dq3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 alternative toggle bit (dq2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 8. status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 8. data polling flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 9. data toggle flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 9. absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 10. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 10. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 11. ac measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 11. device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 12. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 12. read mode ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 13. read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 13. write ac waveforms, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 14. write ac characteristics, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 14. write ac waveforms, chip enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 15. write ac characteristics, chip enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 15. reset/block temporary unprotect ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 16. reset/block temporary unprotect ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 16. accelerated program timing waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 17. 48 lead plastic thin small outline, 12x20 mm, bottom view package outline . . . . . . 29
m29dw324dt, m29dw324db 4/49 table 17. 48 lead plastic thin small outline, 12x20 mm, package mechanical data . . . . . . . . . . 29 figure 18. tfbga63 7x11mm - 6x8 ball array, 0.8mm pitch, bottom view package outline . . . . 30 table 18. tfbga63 7x11mm - 6x8 ball array, 0.8mm pitch, package mechanical data. . . . . . . . 30 figure 19. tfbga48 6x8mm - 6x8 ball array, 0.8mm pitch, bottom view package outline . . . . . 31 table 19. tfbga48 6x8mm - 6x8 ball array, 0.8mm pitch, package mechanical data. . . . . . . . . 31 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 20. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 appendix a. block addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 table 21. top boot block addresses, m29dw324dt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 22. bottom boot block addresses, m29dw324db . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 appendix b. common flash interface (cfi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 23. query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 table 24. cfi query identification string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 table 25. cfi query system interface information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 26. device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 table 27. primary algorithm-specific extended query table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 28. security code area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 appendix c. extended memory block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 factory locked extended block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 customer lockable extended block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 29. extended block address and data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 appendix d. block protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 programmer technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 in-system technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 30. programmer technique bus operations, byte = v ih or v il . . . . . . . . . . . . . . . . . . . . . 43 figure 20. programmer equipment group protect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 21. programmer equipment chip unprotect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 22. in-system equipment group protect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 23. in-system equipment chip unprotect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 31. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
5/49 m29dw324dt, m29dw324db summary description the m29dw324d is a 32 mbit (4mb x8 or 2mb x16) non-volatile memory that can be read, erased and reprogrammed. these operations can be per- formed using a single low voltage (2.7 to 3.6v) supply. on power-up the memory defaults to its read mode where it can be read in the same way as a rom or eprom. the device features an asymmetrical block archi- tecture. the m29dw324d has an array of 8 pa- rameter and 63 main blocks and is divided into two banks, a and b, providing dual bank operations. while programming or erasing in bank a, read op- erations are possible in bank b and vice versa. only one bank at a time is allowed to be in pro- gram or erase mode. the bank architecture is summarized in table 2. m29dw324dt locates the parameter blocks at the top of the memory ad- dress space while the m29dw324db locates the parameter blocks starting from the bottom. m29dw324d has an extra 32 kword (x16 mode) or 64 kbyte (x8 mode) block, the extended block, that can be accessed using a dedicated com- mand. the extended block can be protected and so is useful for storing security information. how- ever the protection is irreversible, once protected the protection cannot be undone. each block can be erased independently so it is possible to preserve valid data while old data is erased. the blocks can be protected to prevent accidental program or erase commands from modifying the memory. program and erase com- mands are written to the command interface of the memory. an on-chip program/erase controller simplifies the process of programming or erasing the memory by taking care of all of the special op- erations that are required to update the memory contents. the end of a program or erase operation can be detected and any error conditions identi- fied. the command set required to control the memory is consistent with jedec standards. chip enable, output enable and write enable sig- nals control the bus operation of the memory. they allow simple connection to most micropro- cessors, often without additional logic. the memory is offered in tsop48 (12x20mm), tfbga63 (7x11mm, 0.8mm pitch) and tfbga48 (6x8mm, 0.8mm pitch) packages. the memory is supplied with all the bits erased (set to 1). figure 2. logic diagram table 1. signal names ai06867b 21 a0-a20 w dq0-dq14 v cc m29dw324dt m29dw324db e v ss 15 g rp dq15aC1 rb v pp /wp byte a0-a20 address inputs dq0-dq7 data inputs/outputs dq8-dq14 data inputs/outputs dq15aC1 data input/output or address input e chip enable g output enable w write enable rp reset/block temporary unprotect rb ready/busy output byte byte/word organization select v cc supply voltage v pp /wp v pp /write protect v ss ground nc not connected internally
m29dw324dt, m29dw324db 6/49 figure 3. tsop connections dq3 dq9 dq2 a6 dq0 w a3 rb dq6 a8 a9 dq13 a17 a10 dq14 a2 dq12 dq10 dq15aC1 v cc dq4 dq5 a7 dq7 v pp /wp nc ai06805 m29dw324dt m29dw324db 12 1 13 24 25 36 37 48 dq8 a20 a19 a1 a18 a4 a5 dq1 dq11 g a12 a13 a16 a11 byte a15 a14 v ss e a0 rp v ss
7/49 m29dw324dt, m29dw324db figure 4. tfbga63 connections (top view through package) note: 1. balls are shorted together via the substrate but not connected to the die. 6 5 4 3 2 1 v ss a15 a14 a12 a13 dq3 dq11 dq10 a18 v pp / wp rb dq1 dq9 dq8 dq0 a6 a17 a7 g e a0 a4 a3 dq2 dq6 dq13 dq14 a10 a8 a9 dq4 v cc dq12 dq5 a19 nc rp w a11 dq7 a1 a2 v ss a5 a20 a16 byte c b a e d f g h dq15 aC1 nc (1) nc (1) nc (1) nc (1) nc (1) nc (1) nc (1) nc (1) nc (1) nc (1) nc (1) j k l m 8 7 nc (1) nc (1) nc (1) nc (1) ai05525b
m29dw324dt, m29dw324db 8/49 figure 5. tfbga48 connections (top view through package) table 2. bank architecture bank bank size parameter blocks main blocks no. of blocks block size no. of blocks block size a 16 mbit 8 8kbyte/ 4 kword 31 64kbyte/ 32 kword b 16 mbit 32 64kbyte/ 32 kword 6 5 4 3 2 1 v ss a15 a14 a12 a13 dq3 dq11 dq10 a18 v pp / wp rb dq1 dq9 dq8 dq0 a6 a17 a7 g e a0 a4 a3 dq2 dq6 dq13 dq14 a10 a8 a9 dq4 v cc dq12 dq5 a19 nc rp w a11 dq7 a1 a2 v ss a5 a20 a16 byte c b a e d f g h dq15 aC1 ai08084
9/49 m29dw324dt, m29dw324db figure 6. block addresses (x8) note: 1. used as extended block addresses in extended block mode. 2. also see appendix a, tables 21 and 22 for a full listing of the block addresses. ai06803 64 kbyte or 32 kword 000000h 00ffffh 64 kbyte or 32 kword 3e0000h 3effffh top boot block (x8) address lines a20-a0, dq15a-1 64 kbyte or 32 kword 1f0000h 1fffffh total of 32 main blocks 64 kbyte or 32 kword 200000h 20ffffh 8 kbyte or 4 kword 3fe000h 3fffffh 8 kbyte or 4 kword 3f0000h 3f1fffh total of 31 main blocks total of 8 parameter blocks (1) bank b bank a 8 kbyte or 4 kword 000000h 001fffh 64 kbyte or 32 kword 1f0000h 1fffffh bottom boot block (x8) address lines a20-a0, dq15a-1 8 kbyte or 4 kword 00e000h 00ffffh total of 8 parameter blocks (1) 64 kbyte or 32 kword 010000h 01ffffh 64 kbyte or 32 kword 3f0000h 3fffffh 64 kbyte or 32 kword 200000h 20ffffh total of 31 main blocks total of 32 main blocks bank b bank a
m29dw324dt, m29dw324db 10/49 figure 7. block addresses (x16) note: 1. used as extended block addresses in extended block mode. 2. also see appendix a, tables 21 and 22 for a full listing of the block addresses. ai05555 64 kbyte or 32 kword 000000h 007fffh 64 kbyte or 32 kword 1f0000h 1f7fffh top boot block (x16) address lines a20-a0 64 kbyte or 32 kword 0f8000h 0fffffh total of 32 main blocks 64 kbyte or 32 kword 100000h 107fffh 8 kbyte or 4 kword 1ff000h 1fffffh 8 kbyte or 4 kword 1f8000h 1f8fffh total of 31 main blocks total of 8 parameter blocks (1) bank b bank a 8 kbyte or 4 kword 000000h 000fffh 64 kbyte or 32 kword 0f8000h 0fffffh bottom boot block (x16) address lines a20-a0 8 kbyte or 4 kword 007000h 007fffh total of 8 parameter blocks (1) 64 kbyte or 32 kword 008000h 00ffffh 64 kbyte or 32 kword 1f8000h 1fffffh 64 kbyte or 32 kword 100000h 107fffh total of 31 main blocks total of 32 main blocks bank b bank a
11/49 m29dw324dt, m29dw324db signal descriptions see figure 2, logic diagram, and table 1, signal names, for a brief overview of the signals connect- ed to this device. address inputs (a0-a20). the address inputs select the cells in the memory array to access dur- ing bus read operations. during bus write opera- tions they control the commands sent to the command interface of the program/erase con- troller. data inputs/outputs (dq0-dq7). the data i/o outputs the data stored at the selected address during a bus read operation. during bus write operations they represent the commands sent to the command interface of the program/erase controller. data inputs/outputs (dq8-dq14). the data i/o outputs the data stored at the selected address during a bus read operation when byte is high, v ih . when byte is low, v il , these pins are not used and are high impedance. during bus write operations the command register does not use these bits. when reading the status register these bits should be ignored. data input/output or address input (dq15aC1). when byte is high, v ih , this pin behaves as a data input/output pin (as dq8-dq14). when byte is low, v il , this pin behaves as an address pin; dq15aC1 low will select the lsb of the ad- dressed word, dq15aC1 high will select the msb. throughout the text consider references to the data input/output to include this pin when byte is high and references to the address inputs to in- clude this pin when byte is low except when stated explicitly otherwise. chip enable (e ). the chip enable, e , activates the memory, allowing bus read and bus write op- erations to be performed. when chip enable is high, v ih , all other pins are ignored. output enable (g ). the output enable, g , con- trols the bus read operation of the memory. write enable (w ). the write enable, w , controls the bus write operation of the memorys com- mand interface. v pp/ write protect (v pp /wp ). the v pp /write protect pin provides two functions. the v pp func- tion allows the memory to use an external high voltage power supply to reduce the time required for program operations. this is achieved by by- passing the unlock cycles and/or using the dou- ble word or quadruple byte program commands. the write protect function provides a hardware method of protecting the two outermost boot blocks. when v pp /write protect is low, v il , the memory protects the two outermost boot blocks; program and erase operations in these blocks are ignored while v pp /write protect is low, even when rp is at v id . when v pp /write protect is high, v ih , the memory reverts to the previous protection status of the two outermost boot blocks. program and erase oper- ations can now modify the data in these blocks un- less the blocks are protected using block protection. when v pp /write protect is raised to v pp the mem- ory automatically enters the unlock bypass mode. when v pp /write protect returns to v ih or v il nor- mal operation resumes. during unlock bypass program operations the memory draws i pp from the pin to supply the programming circuits. see the description of the unlock bypass command in the command interface section. the transitions from v ih to v pp and from v pp to v ih must be slower than t vhvpp , see figure 16. never raise v pp /write protect to v pp from any mode except read mode, otherwise the memory may be left in an indeterminate state. the v pp /write protect pin must not be left floating or unconnected or the device may become unreli- able. a 0.1f capacitor should be connected be- tween the v pp /write protect pin and the v ss ground pin to decouple the current surges from the power supply. the pcb track widths must be sufficient to carry the currents required during unlock bypass program, i pp . reset/block temporary unprotect (rp ). the reset/block temporary unprotect pin can be used to apply a hardware reset to the memory or to temporarily unprotect all blocks that have been protected. note that if v pp /wp is at v il , then the two outer- most boot blocks will remain protected even if rp is at v id . a hardware reset is achieved by holding reset/ block temporary unprotect low, v il , for at least t plpx . after reset/block temporary unprotect goes high, v ih , the memory will be ready for bus read and bus write operations after t phel or t rhel , whichever occurs last. see the ready/busy output section, table 16 and figure 15, reset/ temporary unprotect ac characteristics for more details. holding rp at v id will temporarily unprotect the protected blocks in the memory. program and erase operations on all blocks will be possible. the transition from v ih to v id must be slower than t phphh . ready/busy output (rb ). the ready/busy pin is an open-drain output that can be used to identify when the device is performing a program or erase operation. during program or erase operations
m29dw324dt, m29dw324db 12/49 ready/busy is low, v ol . ready/busy is high-im- pedance during read mode, auto select mode and erase suspend mode. after a hardware reset, bus read and bus write operations cannot begin until ready/busy be- comes high-impedance. see table 16 and figure 15, reset/temporary unprotect ac characteris- tics. the use of an open-drain output allows the ready/ busy pins from several memories to be connected to a single pull-up resistor. a low will then indicate that one, or more, of the memories is busy. byte/word organization select (byte ). the byte/word organization select pin is used to switch between the x8 and x16 bus modes of the memory. when byte/word organization select is low, v il , the memory is in x8 mode, when it is high, v ih , the memory is in x16 mode. v cc supply voltage (2.7v to 3.6v). v cc pro- vides the power supply for all operations (read, program and erase). the command interface is disabled when the v cc supply voltage is less than the lockout voltage, v lko . this prevents bus write operations from ac- cidentally damaging the data during power up, power down and power surges. if the program/ erase controller is programming or erasing during this time then the operation aborts and the memo- ry contents being altered will be invalid. a 0.1f capacitor should be connected between the v cc supply voltage pin and the v ss ground pin to decouple the current surges from the power supply. the pcb track widths must be sufficient to carry the currents required during program and erase operations, i cc3 . v ss ground. v ss is the reference for all voltage measurements. the device features two v ss pins which must be both connected to the system ground.
13/49 m29dw324dt, m29dw324db bus operations there are five standard bus operations that control the device. these are bus read, bus write, out- put disable, standby and automatic standby. the dual bank architecture of the m29dw324d allows read/write operations in bank a, while read operations are being executed in bank b or vice versa. write operations are only allowed in one bank at a time. see tables 3 and 4, bus operations, for a summa- ry. typically glitches of less than 5ns on chip en- able or write enable are ignored by the memory and do not affect bus operations. bus read. bus read operations read from the memory cells, or specific registers in the com- mand interface. a valid bus read operation in- volves setting the desired address on the address inputs, applying a low signal, v il , to chip enable and output enable and keeping write enable high, v ih . the data inputs/outputs will output the value, see figure 12, read mode ac waveforms, and table 13, read ac characteristics, for details of when the output becomes valid. bus write. bus write operations write to the command interface. a valid bus write operation begins by setting the desired address on the ad- dress inputs. the address inputs are latched by the command interface on the falling edge of chip enable or write enable, whichever occurs last. the data inputs/outputs are latched by the com- mand interface on the rising edge of chip enable or write enable, whichever occurs first. output en- able must remain high, v ih , during the whole bus write operation. see figures 13 and 14, write ac waveforms, and tables 14 and 15, write ac characteristics, for details of the timing require- ments. output disable. the data inputs/outputs are in the high impedance state when output enable is high, v ih . standby. when chip enable is high, v ih , the memory enters standby mode and the data in- puts/outputs pins are placed in the high-imped- ance state. to reduce the supply current to the standby supply current, i cc2 , chip enable should be held within v cc 0.2v. for the standby current level see table 12, dc characteristics. during program or erase operations the memory will continue to use the program/erase supply current, i cc3 , for program or erase operations un- til the operation completes. automatic standby. if cmos levels (v cc 0.2v) are used to drive the bus and the bus is inactive for 300ns or more the memory enters automatic standby where the internal supply current is re- duced to the standby supply current, i cc2 . the data inputs/outputs will still output data if a bus read operation is in progress. special bus operations additional bus operations can be performed to read the electronic signature and also to apply and remove block protection. these bus opera- tions are intended for use by programming equip- ment and are not usually used in applications. they require v id to be applied to some pins. electronic signature. the memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. these codes can be read by applying the signals listed in tables 3 and 4, bus operations. block protect and chip unprotect. groups of blocks can be protected against accidental pro- gram or erase. the protection groups are shown in appendix a, tables 21 and 22, block address- es. the whole chip can be unprotected to allow the data inside the blocks to be changed. the v pp /write protect pin can be used to protect the two outermost boot blocks. when v pp /write protect is at v il the two outermost boot blocks are protected and remain protected regardless of the block protection status or the reset/block tem- porary unprotect pin status. block protect and chip unprotect operations are described in appendix d.
m29dw324dt, m29dw324db 14/49 table 3. bus operations, byte = v il note: x = v il or v ih . table 4. bus operations, byte = v ih note: x = v il or v ih . operation e g w address inputs dq15aC1, a0-a20 data inputs/outputs dq14-dq8 dq7-dq0 bus read v il v il v ih cell address hi-z data output bus write v il v ih v il command address hi-z data input output disable x v ih v ih x hi-z hi-z standby v ih x x x hi-z hi-z read manufacturer code v il v il v ih a0 = v il , a1 = v il , a9 = v id , others v il or v ih hi-z 20h read device code v il v il v ih a0 = v ih , a1 = v il , a9 = v id , others v il or v ih hi-z 5ch (m29dw324dt) 5dh (m29dw324db) extended memory block verify code v il v il v ih a0 = v ih , a1 = v ih , a6 = v il , a9 = v id , others v il or v ih hi-z 81h (factory locked) 01h (not factory locked) operation e g w address inputs a0-a20 data inputs/outputs dq15aC1, dq14-dq0 bus read v il v il v ih cell address data output bus write v il v ih v il command address data input output disable x v ih v ih x hi-z standby v ih x x x hi-z read manufacturer code v il v il v ih a0 = v il , a1 = v il , a9 = v id , others v il or v ih 0020h read device code v il v il v ih a0 = v ih , a1 = v il , a9 = v id , others v il or v ih 225ch (m29dw324dt) 225dh (m29dw324db) extended memory block verify code v il v il v ih a0 = v ih , a1 = v ih , a6 = v il , a9 = v id , others v il or v ih 81h (factory locked) 01h (not factory locked)
15/49 m29dw324dt, m29dw324db command interface all bus write operations to the memory are inter- preted by the command interface. commands consist of one or more sequential bus write oper- ations. failure to observe a valid sequence of bus write operations will result in the memory return- ing to read mode. the long command sequences are imposed to maximize data security. the address used for the commands changes de- pending on whether the memory is in 16-bit or 8- bit mode. see either table 5, or 6, depending on the configuration that is being used, for a summary of the commands. read/reset command the read/reset command returns the memory to its read mode where it behaves like a rom or eprom. it also resets the errors in the status register. either one or three bus write operations can be used to issue the read/reset command. the read/reset command can be issued, be- tween bus write cycles before the start of a pro- gram or erase operation, to return the device to read mode. if the read/reset command is issued during the timeout of a block erase operation then the memory will take up to 10s to abort. during the abort period no valid data can be read from the memory. the read/reset command will not abort an erase operation when issued while in erase suspend. auto select command the auto select command is used to read the manufacturer code, the device code, the block protection status and the extended memory block verify code. it can be addressed to either bank. three consecutive bus write operations are re- quired to issue the auto select command. the fi- nal write cycle must be addressed to one of the banks. once the auto select command is issued bus read operations to the bank where the com- mand was issued output the auto select data. bus read operations to the other bank will output the contents of the memory array. the memory re- mains in auto select mode until a read/reset or cfi query command is issued. in auto select mode the manufacturer code can be read using a bus read operation with a0 = v il and a1 = v il and a20 = bank address. the other address bits may be set to either v il or v ih . the device code can be read using a bus read operation with a0 = v ih and a1 = v il and a20 = bank address. the other address bits may be set to either v il or v ih . the block protection status of each block can be read using a bus read operation with a0 = v il , a1 = v ih , a20 = bank address and a12-a17 spec- ifying the address of the block inside the bank. the other address bits may be set to either v il or v ih . if the addressed block is protected then 01h is output on data inputs/outputs dq0-dq7, other- wise 00h is output. read cfi query command the read cfi query command is used to read data from the common flash interface (cfi) memory area. this command is valid when the de- vice is in the read array mode, or when the device is in autoselected mode. one bus write cycle is required to issue the read cfi query command. once the command is is- sued subsequent bus read operations read from the common flash interface memory area. the read/reset command must be issued to re- turn the device to the previous mode (the read ar- ray mode or autoselected mode). a second read/ reset command would be needed if the device is to be put in the read array mode from autoselect- ed mode. see appendix b, tables 23, 24, 25, 26, 27 and 28 for details on the information contained in the common flash interface (cfi) memory area. program command the program command can be used to program a value to one address in the memory array at a time. the command requires four bus write oper- ations, the final write operation latches the ad- dress and data, and starts the program/erase controller. if the address falls in a protected block then the program command is ignored, the data remains unchanged. the status register is never read and no error condition is given. during the program operation the memory will ig- nore all commands. it is not possible to issue any command to abort or pause the operation. after programming has started, bus read operations in the bank being programmed output the status register content, while bus read operations to the other bank output the contents of the memory array. see the section on the status register for more details. typical program times are given in table 7. after the program operation has completed the memory will return to the read mode, unless an error has occurred. when an error occurs bus read operations to the bank where the command was issued will continue to output the status reg- ister. a read/reset command must be issued to reset the error condition and return to read mode. note that the program command cannot change a bit set at 0 back to 1. one of the erase com- mands must be used to set all the bits in a block or in the whole memory from 0 to 1.
m29dw324dt, m29dw324db 16/49 fast program commands there are two fast program commands available to improve the programming throughput, by writing several adjacent words or bytes in parallel. the quadruple byte program command is available for x8 operations, while the double word program command is available for x16 operations. quadruple byte program command. the qua- druple byte program command is used to write a page of four adjacent bytes in parallel. the four bytes must differ only for addresses a0, dq15a-1. five bus write cycles are necessary to issue the quadruple byte program command. n the first bus cycle sets up the quadruple byte program command. n the second bus cycle latches the address and the data of the first byte to be written. n the third bus cycle latches the address and the data of the second byte to be written. n the fourth bus cycle latches the address and the data of the third byte to be written. n the fifth bus cycle latches the address and the data of the fourth byte to be written and starts the program/erase controller. double word program command. the double word program command is used to write a page of two adjacent words in parallel. the two words must differ only for the address a0. three bus write cycles are necessary to issue the double word program command. n the first bus cycle sets up the double word program command. n the second bus cycle latches the address and the data of the first word to be written. n the third bus cycle latches the address and the data of the second word to be written and starts the program/erase controller. only one bank can be programmed at any one time. the other bank must be in read mode or erase suspend. programming should not be attempted when v pp is not at v pph . after programming has started, bus read opera- tions in the bank being programmed output the status register content, while bus read opera- tions to the other bank output the contents of the memory array. after the program operation has completed the memory will return to the read mode, unless an error has occurred. when an error occurs bus read operations to the bank where the command was issued will continue to output the status reg- ister. a read/reset command must be issued to reset the error condition and return to read mode. note that the fast program commands cannot change a bit set at 0 back to 1. one of the erase commands must be used to set all the bits in a block or in the whole memory from 0 to 1. typical program times are given in table 7, pro- gram, erase times and program/erase endur- ance cycles. unlock bypass command. the unlock bypass command is used in conjunc- tion with the unlock bypass program command to program the memory faster than with the standard program commands. when the cycle time to the device is long (as with some eprom program- mers) considerable time saving can be made by using these commands. three bus write opera- tions are required to issue the unlock bypass command. once the unlock bypass command has been is- sued the bank enters unlock bypass mode. the unlock bypass program command can then be is- sued to program addresses within the bank, or the unlock bypass reset command can be issued to return the bank to read mode. in unlock bypass mode the memory can be read as if in read mode. when v pp is applied to the v pp /write protect pin the memory automatically enters the unlock by- pass mode and the unlock bypass program com- mand can be issued immediately. unlock bypass program command. the unlock bypass program command can be used to program one address in the memory array at a time. the command requires two bus write operations, the final write operation latches the ad- dress and data, and starts the program/erase controller. the program operation using the unlock bypass program command behaves identically to the pro- gram operation using the program command. the operation cannot be aborted, a bus read opera- tion to the bank where the command was issued outputs the status register. see the program command for details on the behavior. unlock bypass reset command. the unlock bypass reset command can be used to return to read/reset mode from unlock bypass mode. two bus write operations are required to issue the unlock bypass reset command. read/ reset command does not exit from unlock bypass mode. chip erase command. the chip erase command can be used to erase the entire chip. six bus write operations are re- quired to issue the chip erase command and start the program/erase controller. if any blocks are protected then these are ignored and all the other blocks are erased. if all of the
17/49 m29dw324dt, m29dw324db blocks are protected the chip erase operation ap- pears to start but will terminate within about 100s, leaving the data unchanged. no error condition is given when protected blocks are ignored. during the erase operation the memory will ignore all commands, including the erase suspend com- mand. it is not possible to issue any command to abort the operation. typical chip erase times are given in table 7. all bus read operations during the chip erase operation will output the status register on the data inputs/outputs. see the sec- tion on the status register for more details. after the chip erase operation has completed the memory will return to the read mode, unless an error has occurred. when an error occurs the memory will continue to output the status regis- ter. a read/reset command must be issued to re- set the error condition and return to read mode. the chip erase command sets all of the bits in un- protected blocks of the memory to 1. all previous data is lost. block erase command. the block erase command can be used to erase a list of one or more blocks in a bank. it sets all of the bits in the unprotected selected blocks to 1. all previous data in the selected blocks is lost. six bus write operations are required to select the first block in the list. each additional block in the list can be selected by repeating the sixth bus write operation using the address of the additional block. all blocks must belong to the same bank; if a block belonging to the other bank is given it will not be erased. the block erase operation starts the program/erase controller after a time-out pe- riod of 50s after the last bus write operation. once the program/erase controller starts it is not possible to select any more blocks. each addition- al block must therefore be selected within 50s of the last block. the 50s timer restarts when an ad- ditional block is selected. after the sixth bus write operation a bus read operation within the same bank will output the status register. see the sta- tus register section for details on how to identify if the program/erase controller has started the block erase operation. if any selected blocks are protected then these are ignored and all the other selected blocks are erased. if all of the selected blocks are protected the block erase operation appears to start but will terminate within about 100s, leaving the data un- changed. no error condition is given when protect- ed blocks are ignored. during the block erase operation the memory will ignore all commands except the erase suspend command and the read/reset command which is only accepted during the 50s time-out period. typical block erase times are given in table 7. after the erase operation has started all bus read operations to the bank being erased will output the status register on the data inputs/outputs. see the section on the status register for more details. after the block erase operation has completed the memory will return to the read mode, unless an error has occurred. when an error occurs bus read operations to the bank where the command was issued will continue to output the status reg- ister. a read/reset command must be issued to reset the error condition and return to read mode. erase suspend command. the erase suspend command may be used to temporarily suspend a block erase operation and return the memory to read mode. the command requires one bus write operation. the program/erase controller will suspend within the erase suspend latency time of the erase sus- pend command being issued. once the program/ erase controller has stopped the memory will be set to read mode and the erase will be suspend- ed. if the erase suspend command is issued dur- ing the period when the memory is waiting for an additional block (before the program/erase con- troller starts) then the erase is suspended immedi- ately and will start immediately when the erase resume command is issued. it is not possible to select any further blocks to erase after the erase resume. during erase suspend it is possible to read and program cells in blocks that are not being erased; both read and program operations behave as normal on these blocks. if any attempt is made to program in a protected block or in the suspended block then the program command is ignored and the data remains unchanged. the status register is not read and no error condition is given. read- ing from blocks that are being erased will output the status register. it is also possible to issue the auto select, read cfi query and unlock bypass commands during an erase suspend. the read/reset command must be issued to return the device to read array mode before the resume command will be ac- cepted. during erase suspend a bus read operation to the extended block will output the extended block data. erase resume command. the erase resume command must be used to re- start the program/erase controller after an erase suspend. the device must be in read array mode before the resume command will be accepted. an erase can be suspended and resumed more than once.
m29dw324dt, m29dw324db 18/49 enter extended block command the m29dw324d has an extra 64kbyte block (extended block) that can only be accessed using the enter extended block command. three bus write cycles are required to issue the extended block command. once the command has been is- sued the device enters extended block mode where all bus read or program operations to the boot block addresses access the extended block. the extended block (with the same address as the boot block) cannot be erased, and can be treated as one-time programmable (otp) memo- ry. in extended block mode the boot blocks are not accessible. in extended block mode dual op- erations are possible, with the extended block mapped in bank a. when in extended block mode, erase commands in bank a are not al- lowed. to exit from the extended block mode the exit ex- tended block command must be issued. the extended block can be protected, however once protected the protection cannot be undone. exit extended block command. the exit extended block command is used to exit from the extended block mode and return the de- vice to read mode. four bus write operations are required to issue the command. block protect and chip unprotect commands. groups of blocks can be protected against acci- dental program or erase. the protection groups are shown in appendix a, tables 21 and 22, block addresses. the whole chip can be unprotected to allow the data inside the blocks to be changed. block protect and chip unprotect operations are described in appendix d. table 5. commands, 16-bit mode, byte = v ih note: x dont care, pa program address, pd program data, ba any address in the block, bka bank address. all values in the table are i n hexadecimal. the command interface only uses aC1, a0-a10 and dq0-dq7 to verify the commands; a11-a20, dq8-dq14 and dq15 are dont care. dq15aC1 is aC1 when byte is v il or dq15 when byte is v ih . command length bus write operations 1st 2nd 3rd 4th 5th 6th addr data addr data addr data addr data addr data addr data read/reset 1x f0 3 555 aa 2aa 55 x f0 auto select 3 555 aa 2aa 55 (bka) 555 90 program 4 555 aa 2aa 55 555 a0 pa pd double word program 3 555 50 pa0 pd0 pa1 pd1 unlock bypass 3 555 aa 2aa 55 555 20 unlock bypass program 2x a0papd unlock bypass reset 2 x 90 x 00 chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 block erase 6+ 555 aa 2aa 55 555 80 555 aa 2aa 55 ba 30 erase suspend 1 bka b0 erase resume 1 bka 30 read cfi query 1 55 98 enter extended block 3 555 aa 2aa 55 555 88 exit extended block 4 555 aa 2aa 55 555 90 x 00
19/49 m29dw324dt, m29dw324db table 6. commands, 8-bit mode, byte = v il note: x dont care, pa program address, pd program data, ba any address in the block. all values in the table are in hexadecimal. the command interface only uses aC1, a0-a10 and dq0-dq7 to verify the commands; a11-a20, dq8-dq14 and dq15 are dont care. dq15aC1 is aC1 when byte is v il or dq15 when byte is v ih . table 7. program, erase times and program, erase endurance cycles note: 1. typical values measured at room temperature and nominal voltages. 2. sampled, but not 100% tested. 3. maximum value measured at worst case conditions for both temperature and v cc after 100,00 program/erase cycles. 4. maximum value measured at worst case conditions for both temperature and v cc . command length bus write operations 1st 2nd 3rd 4th 5th 6th add data add data add data add data add data add data read/reset 1x f0 3 aaa aa 555 55 x f0 auto select 3 aaa aa 555 55 (bka) aaa 90 program 4 aaa aa 555 55 aaa a0 pa pd quadruple byte program 5 aaa 55 pa0 pd0 pa1 pd1 pa2 pd2 pa3 pd3 unlock bypass 3 aaa aa 555 55 aaa 20 unlock bypass program 2 x a0 pa pd unlock bypass reset 2 x 90 x 00 chip erase 6 aaa aa 555 55 aaa 80 aaa aa 555 55 aaa 10 block erase 6+ aaa aa 555 55 aaa 80 aaa aa 555 55 ba 30 erase suspend 1 bka b0 erase resume 1 bka 30 read cfi query 1 aa 98 enter extended block 3 aaa aa 555 55 aaa 88 exit extended block 4 aaa aa 555 55 aaa 90 x 00 parameter min typ (1, 2) max (2) unit chip erase 40 200 (3) s block erase (64 kbytes) 0.8 6 (3) s erase suspend latency time 50 (4) s program (byte or word) 10 200 (4) s double word program (byte or word) 10 200 (3) s chip program (byte by byte) 40 200 (3) s chip program (word by word) 20 100 (3) s chip program (quadruple byte or double word) 10 100 s program/erase cycles (per block) 100,000 cycles data retention 20 years
m29dw324dt, m29dw324db 20/49 status register the m29dw324d has two status registers, one for each bank. the status registers provide infor- mation on the current or previous program or erase operations executed in each bank. the var- ious bits convey information and errors on the op- eration. bus read operations from any address within the bank, always read the status register during program and erase operations. it is also read during erase suspend when an address with- in a block being erased is accessed. the bits in the status register are summarized in table 8, status register bits. data polling bit (dq7). the data polling bit can be used to identify whether the program/erase controller has successfully completed its opera- tion or if it has responded to an erase suspend. the data polling bit is output on dq7 when the status register is read. during program operations the data polling bit outputs the complement of the bit being pro- grammed to dq7. after successful completion of the program operation the memory returns to read mode and bus read operations from the ad- dress just programmed output dq7, not its com- plement. during erase operations the data polling bit out- puts 0, the complement of the erased state of dq7. after successful completion of the erase op- eration the memory returns to read mode. in erase suspend mode the data polling bit will output a 1 during a bus read operation within a block being erased. the data polling bit will change from a 0 to a 1 when the program/erase controller has suspended the erase operation. figure 8, data polling flowchart, gives an exam- ple of how to use the data polling bit. a valid ad- dress is the address being programmed or an address within the block being erased. toggle bit (dq6). the toggle bit can be used to identify whether the program/erase controller has successfully completed its operation or if it has re- sponded to an erase suspend. the toggle bit is output on dq6 when the status register is read. during program and erase operations the toggle bit changes from 0 to 1 to 0, etc., with succes- sive bus read operations at any address. after successful completion of the operation the memo- ry returns to read mode. during erase suspend mode the toggle bit will output when addressing a cell within a block being erased. the toggle bit will stop toggling when the program/erase controller has suspended the erase operation. figure 9, data toggle flowchart, gives an exam- ple of how to use the data toggle bit. error bit (dq5). the error bit can be used to identify errors detected by the program/erase controller. the error bit is set to 1 when a pro- gram, block erase or chip erase operation fails to write the correct data to the memory. if the error bit is set a read/reset command must be issued before other commands are issued. the error bit is output on dq5 when the status register is read. note that the program command cannot change a bit set to 0 back to 1 and attempting to do so will set dq5 to 1. a bus read operation to that ad- dress will show the bit is still 0. one of the erase commands must be used to set all the bits in a block or in the whole memory from 0 to 1. erase timer bit (dq3). the erase timer bit can be used to identify the start of program/erase controller operation during a block erase com- mand. once the program/erase controller starts erasing the erase timer bit is set to 1. before the program/erase controller starts the erase timer bit is set to 0 and additional blocks to be erased may be written to the command interface. the erase timer bit is output on dq3 when the status register is read. alternative toggle bit (dq2). the alternative toggle bit can be used to monitor the program/ erase controller during erase operations. the al- ternative toggle bit is output on dq2 when the status register is read. during chip erase and block erase operations the toggle bit changes from 0 to 1 to 0, etc., with successive bus read operations from addresses within the blocks being erased. a protected block is treated the same as a block not being erased. once the operation completes the memory returns to read mode. during erase suspend the alternative toggle bit changes from 0 to 1 to 0, etc. with successive bus read operations from addresses within the blocks being erased. bus read operations to ad- dresses within blocks not being erased will output the memory cell data as if in read mode. after an erase operation that causes the error bit to be set the alternative toggle bit can be used to identify which block or blocks have caused the er- ror. the alternative toggle bit changes from 0 to 1 to 0, etc. with successive bus read opera- tions from addresses within blocks that have not erased correctly. the alternative toggle bit does not change if the addressed block has erased cor- rectly.
21/49 m29dw324dt, m29dw324db table 8. status register bits note: unspecified data bits should be ignored. figure 8. data polling flowchart figure 9. data toggle flowchart operation address dq7 dq6 dq5 dq3 dq2 rb program bank address dq7 toggle 0 CC0 program during erase suspend bank address dq7 toggle 0 C C 0 program error bank address dq7 toggle 1 C C 0 chip erase any address 0 toggle 0 1 toggle 0 block erase before timeout erasing block 0 toggle 0 0 toggle 0 non-erasing block 0 toggle 0 0 no toggle 0 block erase erasing block 0 toggle 0 1 toggle 0 non-erasing block 0 toggle 0 1 no toggle 0 erase suspend erasing block 1 no toggle 0 C toggle 1 non-erasing block data read as normal 1 erase error good block address 0 toggle 1 1 no toggle 0 faulty block address 0 toggle 1 1 toggle 0 read dq5 & dq7 at valid address start read dq7 at valid address fail pass ai90194 dq7 = data yes no yes no dq5 = 1 dq7 = data yes no read dq6 start read dq6 twice fail pass ai90195b dq6 = toggle no no yes yes dq5 = 1 no yes dq6 = toggle read dq5 & dq6
m29dw324dt, m29dw324db 22/49 maximum rating stressing the device above the rating listed in the absolute maximum ratings table may cause per- manent damage to the device. exposure to abso- lute maximum rating conditions for extended periods may affect device reliability. these are stress ratings only and operation of the device at these or any other conditions above those indicat- ed in the operating sections of this specification is not implied. refer also to the stmicroelectronics sure program and other relevant quality docu- ments. table 9. absolute maximum ratings note: 1. minimum voltage may undershoot to C2v during transition and for less than 20ns during transitions. 2. maximum voltage may overshoot to v cc +2v during transition and for less than 20ns during transitions. 3. v pp must not remain at 12v for more than a total of 80hrs. symbol parameter min max unit t bias temperature under bias C50 125 c t stg storage temperature C65 150 c v io input or output voltage (1,2) C0.6 v cc +0.6 v v cc supply voltage C0.6 4 v v id identification voltage C0.6 13.5 v v pp (3) program voltage C0.6 13.5 v
23/49 m29dw324dt, m29dw324db dc and ac parameters this section summarizes the operating measure- ment conditions, and the dc and ac characteris- tics of the device. the parameters in the dc and ac characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in table 10, operating and ac measurement conditions. designers should check that the operating conditions in their circuit match the operating conditions when rely- ing on the quoted parameters. table 10. operating and ac measurement conditions figure 10. ac measurement i/o waveform figure 11. ac measurement load circuit table 11. device capacitance note: sampled only, not 100% tested. parameter m29dw324d unit 70 90 min max min max v cc supply voltage 3.0 3.6 2.7 3.6 v ambient operating temperature C40 85 C40 85 c load capacitance (c l ) 30 30 pf input rise and fall times 10 10 ns input pulse voltages 0 to v cc 0 to v cc v input and output timing ref. voltages v cc /2 v cc /2 v ai05557 v cc 0v v cc /2 ai05558 c l c l includes jig capacitance device under test 25k w v cc 25k w v cc 0.1f v pp 0.1f symbol parameter test condition min max unit c in input capacitance v in = 0v 6pf c out output capacitance v out = 0v 12 pf
m29dw324dt, m29dw324db 24/49 table 12. dc characteristics note: 1. sampled only, not 100% tested. 2. in dual operations the supply current will be the sum of i cc1 (read) and i cc3 (program/erase). symbol parameter test condition min max unit i li input leakage current 0v v in v cc 1 a i lo output leakage current 0v v out v cc 1 a i cc1 (2) supply current (read) e = v il , g = v ih , f = 6mhz 10 ma i cc2 supply current (standby) e = v cc 0.2v, rp = v cc 0.2v 100 a i cc3 (1,2) supply current (program/ erase) program/erase controller active v pp /wp = v il or v ih 20 ma v pp /wp = v pp 20 ma v il input low voltage C0.5 0.8 v v ih input high voltage 0.7v cc v cc +0.3 v v pp voltage for v pp /wp program acceleration v cc = 3.0v 10% 11.5 12.5 v i pp current for v pp /wp program acceleration v cc = 3.0v 10% 15 ma v ol output low voltage i ol = 1.8ma 0.45 v v oh output high voltage i oh = C100 a v cc C0.4 v v id identification voltage 11.5 12.5 v v lko program/erase lockout supply voltage 1.8 2.3 v
25/49 m29dw324dt, m29dw324db figure 12. read mode ac waveforms table 13. read ac characteristics note: 1. sampled only, not 100% tested. symbol alt parameter test condition m29dw324d unit 70 90 t avav t rc address valid to next address valid e = v il , g = v il min 70 90 ns t avqv t acc address valid to output valid e = v il , g = v il max 70 90 ns t elqx (1) t lz chip enable low to output transition g = v il min 0 0 ns t elqv t ce chip enable low to output valid g = v il max 70 90 ns t glqx (1) t olz output enable low to output transition e = v il min 0 0 ns t glqv t oe output enable low to output valid e = v il max 30 35 ns t ehqz (1) t hz chip enable high to output hi-z g = v il max 25 30 ns t ghqz (1) t df output enable high to output hi-z e = v il max 25 30 ns t ehqx t ghqx t axqx t oh chip enable, output enable or address transition to output transition min 0 0 ns t elbl t elbh t elfl t elfh chip enable to byte low or high max 5 5 ns t blqz t flqz byte low to output hi-z max 25 30 ns t bhqv t fhqv byte high to output valid max 30 40 ns ai05559 tavav tavqv taxqx telqx tehqz tglqv tglqx tghqx valid a0-a20/ aC1 g dq0-dq7/ dq8-dq15 e telqv tehqx tghqz valid tbhqv telbl/telbh tblqz byte
m29dw324dt, m29dw324db 26/49 figure 13. write ac waveforms, write enable controlled table 14. write ac characteristics, write enable controlled note: 1. sampled only, not 100% tested. symbol alt parameter m29dw324d unit 70 90 t avav t wc address valid to next address valid min 70 90 ns t elwl t cs chip enable low to write enable low min 0 0 ns t wlwh t wp write enable low to write enable high min 45 50 ns t dvwh t ds input valid to write enable high min 45 50 ns t whdx t dh write enable high to input transition min 0 0 ns t wheh t ch write enable high to chip enable high min 0 0 ns t whwl t wph write enable high to write enable low min 30 30 ns t avwl t as address valid to write enable low min 0 0 ns t wlax t ah write enable low to address transition min 45 50 ns t ghwl output enable high to write enable low min 0 0 ns t whgl t oeh write enable high to output enable low min 0 0 ns t whrl (1) t busy program/erase valid to rb low max 30 35 ns t vchel t vcs v cc high to chip enable low min 50 50 s ai05560 e g w a0-a20/ aC1 dq0-dq7/ dq8-dq15 valid valid v cc tvchel twheh twhwl telwl tavwl twhgl twlax twhdx tavav tdvwh twlwh tghwl rb twhrl
27/49 m29dw324dt, m29dw324db figure 14. write ac waveforms, chip enable controlled table 15. write ac characteristics, chip enable controlled note: 1. sampled only, not 100% tested. symbol alt parameter m29dw324d unit 70 90 t avav t wc address valid to next address valid min 70 90 ns t wlel t ws write enable low to chip enable low min 0 0 ns t eleh t cp chip enable low to chip enable high min 45 50 ns t dveh t ds input valid to chip enable high min 45 50 ns t ehdx t dh chip enable high to input transition min 0 0 ns t ehwh t wh chip enable high to write enable high min 0 0 ns t ehel t cph chip enable high to chip enable low min 30 30 ns t avel t as address valid to chip enable low min 0 0 ns t elax t ah chip enable low to address transition min 45 50 ns t ghel output enable high chip enable low min 0 0 ns t ehgl t oeh chip enable high to output enable low min 0 0 ns t ehrl (1) t busy program/erase valid to rb low max 30 35 ns t vchwl t vcs v cc high to write enable low min 50 50 s ai05561 e g w a0-a20/ aC1 dq0-dq7/ dq8-dq15 valid valid v cc tvchwl tehwh tehel twlel tavel tehgl telax tehdx tavav tdveh teleh tghel rb tehrl
m29dw324dt, m29dw324db 28/49 figure 15. reset/block temporary unprotect ac waveforms table 16. reset/block temporary unprotect ac characteristics note: 1. sampled only, not 100% tested. figure 16. accelerated program timing waveforms symbol alt parameter m29dw324d unit 70 90 t phwl (1) t phel t phgl (1) t rh rp high to write enable low, chip enable low, output enable low min 50 50 ns t rhwl (1) t rhel (1) t rhgl (1) t rb rb high to write enable low, chip enable low, output enable low min 0 0 ns t plpx t rp rp pulse width min 500 500 ns t plyh t ready rp low to read mode max 50 50 s t phphh (1) t vidr rp rise time to v id min 500 500 ns t vhvpp (1) v pp rise and fall time min 250 250 ns ai02931b rb w, rp tplpx tphwl, tphel, tphgl tplyh tphphh e, g trhwl, trhel, trhgl ai05563 v pp /wp v pp v il or v ih tvhvpp tvhvpp
29/49 m29dw324dt, m29dw324db package mechanical figure 17. 48 lead plastic thin small outline, 12x20 mm, bottom view package outline note: drawing not to scale. table 17. 48 lead plastic thin small outline, 12x20 mm, package mechanical data symbol millimeters inches typ min max typ min max a 1.200 0.0472 a1 0.100 0.050 0.150 0.0039 0.0020 0.0059 a2 1.000 0.950 1.050 0.0394 0.0374 0.0413 b 0.220 0.170 0.270 0.0087 0.0067 0.0106 c 0.100 0.210 0.0039 0.0083 cp 0.080 0.0031 d1 12.000 11.900 12.100 0.4724 0.4685 0.4764 e 20.000 19.800 20.200 0.7874 0.7795 0.7953 e1 18.400 18.300 18.500 0.7244 0.7205 0.7283 e 0.500 C C 0.0197 C C l 0.600 0.500 0.700 0.0236 0.0197 0.0276 l1 0.800 0.0315 a 305305 tsop-g b e die c l a1 a e1 e a a2 1 24 48 25 d1 l1 cp
m29dw324dt, m29dw324db 30/49 figure 18. tfbga63 7x11mm - 6x8 ball array, 0.8mm pitch, bottom view package outline note: drawing not to scale. table 18. tfbga63 7x11mm - 6x8 ball array, 0.8mm pitch, package mechanical data symbol millimeters inches typ min max typ min max a 1.200 0.0472 a1 0.250 0.0098 a2 0.900 0.0354 b 0.350 0.450 0.0138 0.0177 d 7.000 6.900 7.100 0.2756 0.2717 0.2795 d1 5.600 C C 0.2205 C C ddd C C 0.100 C C 0.0039 e 11.000 10.900 11.100 0.4331 0.4291 0.4370 e1 8.800 C C 0.3465 C C e 0.800 C C 0.0315 C C fd 0.700 C C 0.0276 C C fe 1.100 C C 0.0433 C C sd 0.400 C C 0.0157 C C se 0.400 C C 0.0157 C C e d eb sd se a2 a1 a bga-z33 ddd fd d1 e1 e fe ball "a1"
31/49 m29dw324dt, m29dw324db figure 19. tfbga48 6x8mm - 6x8 ball array, 0.8mm pitch, bottom view package outline note: drawing not to scale. table 19. tfbga48 6x8mm - 6x8 ball array, 0.8mm pitch, package mechanical data symbol millimeters inches typ min max typ min max a 1.200 0.0472 a1 0.260 0.0102 a2 0.900 0.0354 b 0.350 0.450 0.0138 0.0177 d 6.000 5.900 6.100 0.2362 0.2323 0.2402 d1 4.000 C C 0.1575 C C ddd 0.100 0.0039 e 8.000 7.900 8.100 0.3150 0.3110 0.3189 e1 5.600 C C 0.2205 C C e 0.800 C C 0.0315 C C fd 1.000 C C 0.0394 C C fe 1.200 C C 0.0472 C C sd 0.400 C C 0.0157 C C se 0.400 C C 0.0157 C C e1 e d1 d eb a2 a1 a bga-z32 ddd fd fe sd se e ball "a1"
m29dw324dt, m29dw324db 32/49 part numbering table 20. ordering information scheme note: this product is also available with the extended block factory locked. for further details and ordering information contact your nearest st sales office. devices are shipped from the factory with the memory content bits erased to 1. for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest st sales office. example: m29dw324db 70 n 1 t device type m29 architecture d = dual bank operating voltage w = v cc = 2.7 to 3.6v device function 324d = 32 mbit (x8/x16), boot block, half-half partitioning array matrix t = top boot b = bottom boot speed 70 = 70 ns 90 = 90 ns package n = tsop48: 12 x 20mm za = tfbga63: 7 x 11mm, 0.80mm pitch ze = tfgba48: 6 x 8mm, 0.80mm pitch temperature range 1 = 0 to 70 c 6 = C40 to 85 c option blank = standard packing t = tape & reel packing e = lead-free package, standard packing f = lead-free package, tape & reel packing
33/49 m29dw324dt, m29dw324db appendix a. block addresses table 21. top boot block addresses, m29dw324dt bank block (kbytes/ kwords) protection block group (x8) (x16) bank b 0 64/32 protection group 000000hC00ffffh 000000hC07fffh 1 64/32 protection group 010000hC01ffffh 008000hC0ffffh 2 64/32 020000hC02ffffh 010000hC17fffh 3 64/32 030000hC03ffffh 018000hC01ffffh 4 64/32 protection group 040000hC04ffffh 020000hC027fffh 5 64/32 050000hC05ffffh 028000hC02ffffh 6 64/32 060000hC06ffffh 030000hC037fffh 7 64/32 070000hC07ffffh 038000hC03ffffh 8 64/32 protection group 080000hC08ffffh 040000hC047fffh 9 64/32 090000hC09ffffh 048000hC04ffffh 10 64/32 0a0000hC0affffh 050000hC057fffh 11 64/32 0b0000hC0bffffh 058000hC05ffffh 12 64/32 protection group 0c0000hC0cffffh 060000hC067fffh 13 64/32 0d0000hC0dffffh 068000hC06ffffh 14 64/32 0e0000hC0effffh 070000hC077fffh 15 64/32 0f0000hC0fffffh 078000hC07ffffh 16 64/32 protection group 100000hC10ffffh 080000hC087fffh 17 64/32 110000hC11ffffh 088000hC08ffffh 18 64/32 120000hC12ffffh 090000hC097fffh 19 64/32 130000hC13ffffh 098000hC09ffffh 20 64/32 protection group 140000hC14ffffh 0a0000hC0a7fffh 21 64/32 150000hC15ffffh 0a8000hC0affffh 22 64/32 160000hC16ffffh 0b0000hC0b7fffh 23 64/32 170000hC17ffffh 0b8000hC0bffffh 24 64/32 protection group 180000hC18ffffh 0c0000hC0c7fffh 25 64/32 190000hC19ffffh 0c8000hC0cffffh 26 64/32 1a0000hC1affffh 0d0000hC0d7fffh 27 64/32 1b0000hC1bffffh 0d8000hC0dffffh 28 64/32 protection group 1c0000hC1cffffh 0e0000hC0e7fffh 29 64/32 1d0000hC1dffffh 0e8000hC0effffh 30 64/32 1e0000hC1effffh 0f0000hC0f7fffh 31 64/32 1f0000hC1fffffh 0f8000hC0fffffh
m29dw324dt, m29dw324db 34/49 bank a 32 64/32 protection group 200000hC20ffffh 100000hC107fffh 33 64/32 210000hC21ffffh 108000hC10ffffh 34 64/32 220000hC22ffffh 110000hC117fffh 35 64/32 230000hC23ffffh 118000hC11ffffh 36 64/32 protection group 240000hC24ffffh 120000hC127fffh 37 64/32 250000hC25ffffh 128000hC12ffffh 38 64/32 260000hC26ffffh 130000hC137fffh 39 64/32 270000hC27ffffh 138000hC13ffffh 40 64/32 protection group 280000hC28ffffh 140000hC147fffh 41 64/32 290000hC29ffffh 148000hC14ffffh 42 64/32 2a0000hC2affffh 150000hC157fffh 43 64/32 2b0000hC2bffffh 158000hC15ffffh 44 64/32 protection group 2c0000hC2cffffh 160000hC167fffh 45 64/32 2d0000hC2dffffh 168000hC16ffffh 46 64/32 2e0000hC2effffh 170000hC177fffh 47 64/32 2f0000hC2fffffh 178000hC17ffffh 48 64/32 protection group 300000hC30ffffh 180000hC187fffh 49 64/32 310000hC31ffffh 188000hC18ffffh 50 64/32 320000hC32ffffh 190000hC197fffh 51 64/32 330000hC33ffffh 198000hC19ffffh 52 64/32 protection group 340000hC34ffffh 1a0000hC1a7fffh 53 64/32 350000hC35ffffh 1a8000hC1affffh 54 64/32 360000hC36ffffh 1b0000hC1b7fffh 55 64/32 370000hC37ffffh 1b8000hC1bffffh 56 64/32 protection group 380000hC38ffffh 1c0000hC1c7fffh 57 64/32 390000hC39ffffh 1c8000hC1cffffh 58 64/32 3a0000hC3affffh 1d0000hC1d7fffh 59 64/32 3b0000hC3bffffh 1d8000hC1dffffh 60 64/32 protection group 3c0000hC3cffffh 1e0000hC1e7fffh 61 64/32 3d0000hC3dffffh 1e8000hC1effffh 62 64/32 3e0000hC3effffh 1f0000hC1f7fffh bank block (kbytes/ kwords) protection block group (x8) (x16)
35/49 m29dw324dt, m29dw324db note: 1. used as the extended block addresses in extended block mode. bank a 63 8/4 protection group 3f0000hC3f1fffh (1) 1f8000hC1f8fffh (1) 64 8/4 protection group 3f2000hC3f3fffh (1) 1f9000hC1f9fffh (1) 65 8/4 protection group 3f4000hC3f5fffh (1) 1fa000hC1fafffh (1) 66 8/4 protection group 3f6000hC3f7fffh (1) 1fb000hC1fbfffh (1) 67 8/4 protection group 3f8000hC3f9fffh (1) 1fc000hC1fcfffh (1) 68 8/4 protection group 3fa000hC3fbfffh (1) 1fd000hC1fdfffh (1) 69 8/4 protection group 3fc000hC3fdfffh (1) 1fe000hC1fefffh (1) 70 8/4 protection group 3fe000hC3fffffh (1) 1ff000hC1fffffh (1) bank block (kbytes/ kwords) protection block group (x8) (x16)
m29dw324dt, m29dw324db 36/49 table 22. bottom boot block addresses, m29dw324db bank block (kbytes/ kwords) protection block group (x8) (x16) bank a 0 8/4 protection group 000000h-001fffh (1) 000000hC000fffh (1) 1 8/4 protection group 002000h-003fffh (1) 001000hC001fffh (1) 2 8/4 protection group 004000h-005fffh (1) 002000hC002fffh (1) 3 8/4 protection group 006000h-007fffh (1) 003000hC003fffh (1) 4 8/4 protection group 008000h-009fffh (1) 004000hC004fffh (1) 5 8/4 protection group 00a000h-00bfffh (1) 005000hC005fffh (1) 6 8/4 protection group 00c000h-00dfffh (1) 006000hC006fffh (1) 7 8/4 protection group 00e000h-00ffffh (1) 007000hC007fffh (1) 8 64/32 protection group 010000h-01ffffh 008000hC00ffffh 9 64/32 020000h-02ffffh 010000hC017fffh 10 64/32 030000h-03ffffh 018000hC01ffffh 11 64/32 protection group 040000h-04ffffh 020000hC027fffh 12 64/32 050000h-05ffffh 028000hC02ffffh 13 64/32 060000h-06ffffh 030000hC037fffh 14 64/32 070000h-07ffffh 038000hC03ffffh 15 64/32 protection group 080000h-08ffffh 040000hC047fffh 16 64/32 090000h-09ffffh 048000hC04ffffh 17 64/32 0a0000h-0affffh 050000hC057fffh 18 64/32 0b0000h-0bffffh 058000hC05ffffh 19 64/32 protection group 0c0000h-0cffffh 060000hC067fffh 20 64/32 0d0000h-0dffffh 068000hC06ffffh 21 64/32 0e0000h-0effffh 070000hC077fffh 22 64/32 0f0000h-0fffffh 078000hC07ffffh 23 64/32 protection group 100000h-10ffffh 080000hC087fffh 24 64/32 110000h-11ffffh 088000hC08ffffh 25 64/32 120000h-12ffffh 090000hC097fffh 26 64/32 130000h-13ffffh 098000hC09ffffh 27 64/32 protection group 140000h-14ffffh 0a0000hC0a7fffh 28 64/32 150000h-15ffffh 0a8000hC0affffh 29 64/32 160000h-16ffffh 0b0000hC0b7fffh 30 64/32 170000h-17ffffh 0b8000hC0bffffh
37/49 m29dw324dt, m29dw324db bank a 31 64/32 protection group 180000h-18ffffh 0c0000hC0c7fffh 32 64/32 190000h-19ffffh 0c8000hC0cffffh 33 64/32 1a0000h-1affffh 0d0000hC0d7fffh 34 64/32 1b0000h-1bffffh 0d8000hC0dffffh 35 64/32 protection group 1c0000h-1cffffh 0e0000hC0e7fffh 36 64/32 1d0000h-1dffffh 0e8000hC0effffh 37 64/32 1e0000h-1effffh 0f0000hC0f7fffh 38 64/32 1f0000h-1fffffh 0f8000hC0fffffh bank b 39 64/32 protection group 200000h-20ffffh 100000hC107fffh 40 64/32 210000h-21ffffh 108000hC10ffffh 41 64/32 220000h-22ffffh 110000hC117fffh 42 64/32 230000h-23ffffh 118000hC11ffffh 43 64/32 protection group 240000h-24ffffh 120000hC127fffh 44 64/32 250000h-25ffffh 128000hC12ffffh 45 64/32 260000h-26ffffh 130000hC137fffh 46 64/32 270000h-27ffffh 138000hC13ffffh 47 64/32 protection group 280000h-28ffffh 140000hC147fffh 48 64/32 290000h-29ffffh 148000hC14ffffh 49 64/32 2a0000h-2affffh 150000hC157fffh 50 64/32 2b0000h-2bffffh 158000hC15ffffh 51 64/32 protection group 2c0000h-2cffffh 160000hC167fffh 52 64/32 2d0000h-2dffffh 168000hC16ffffh 53 64/32 2e0000h-2effffh 170000hC177fffh 54 64/32 2f0000h-2fffffh 178000hC17ffffh 55 64/32 protection group 300000h-30ffffh 180000hC187fffh 56 64/32 310000h-31ffffh 188000hC18ffffh 57 64/32 320000h-32ffffh 190000hC197fffh 58 64/32 330000h-33ffffh 198000hC19ffffh 59 64/32 protection group 340000h-34ffffh 1a0000hC1a7fffh 60 64/32 350000h-35ffffh 1a8000hC1affffh 61 64/32 360000h-36ffffh 1b0000hC1b7fffh 62 64/32 370000h-37ffffh 1b8000hC1bffffh bank block (kbytes/ kwords) protection block group (x8) (x16)
m29dw324dt, m29dw324db 38/49 note: 1. used as the extended block addresses in extended block mode. bank b 63 64/32 protection group 380000h-38ffffh 1c0000hC1c7fffh 64 64/32 390000h-39ffffh 1c8000hC1cffffh 65 64/32 3a0000h-3affffh 1d0000hC1d7fffh 66 64/32 3b0000h-3bffffh 1d8000hC1dffffh 67 64/32 protection group 3c0000h-3cffffh 1e0000hC1e7fffh 68 64/32 3d0000h-3dffffh 1e8000hC1effffh 69 64/32 3e0000h-3effffh 1f0000hC1f7fffh 70 64/32 protection group 3f0000h-3fffffh 1f8000hC1fffffh bank block (kbytes/ kwords) protection block group (x8) (x16)
39/49 m29dw324dt, m29dw324db appendix b. common flash interface (cfi) the common flash interface is a jedec ap- proved, standardized data structure that can be read from the flash memory device. it allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the mem- ory. the system can interface easily with the de- vice, enabling the software to upgrade itself when necessary. when the cfi query command is issued the de- vice enters cfi query mode and the data structure is read from the memory. tables 23, 24, 25, 26, 27 and 28 show the addresses used to retrieve the data. the cfi data structure also contains a security area where a 64 bit unique security number is writ- ten (see table 28, security code area). this area can be accessed only in read mode by the final user. it is impossible to change the security num- ber after it has been written by st. table 23. query structure overview note: query data are always presented on the lowest order data outputs. table 24. cfi query identification string note: query data are always presented on the lowest order data outputs (dq7-dq0) only. dq8-dq15 are 0. address sub-section name description x16 x8 10h 20h cfi query identification string command set id and algorithm data offset 1bh 36h system interface information device timing & voltage information 27h 4eh device geometry definition flash device layout 40h 80h primary algorithm-specific extended query table additional information specific to the primary algorithm (optional) 61h c2h security code area 64 bit unique device number address data description value x16 x8 10h 20h 0051h q 11h 22h 0052h query unique ascii string "qry" "r" 12h 24h 0059h "y" 13h 26h 0002h primary algorithm command set and control interface id code 16 bit id code defining a specific algorithm amd compatible 14h 28h 0000h 15h 2ah 0040h address for primary algorithm extended query table (see table 27) p = 40h 16h 2ch 0000h 17h 2eh 0000h alternate vendor command set and control interface id code second vendor - specified algorithm supported na 18h 30h 0000h 19h 32h 0000h address for alternate algorithm extended query table na 1ah 34h 0000h
m29dw324dt, m29dw324db 40/49 table 25. cfi query system interface information table 26. device geometry definition note: the region information contained in addresses 2dh to 34h (or 5ah to 68h) is correct for the m29dw324db. for the m29dw324dt the regions must be reversed. address data description value x16 x8 1bh 36h 0027h v cc logic supply minimum program/erase voltage bit 7 to 4 bcd value in volts bit 3 to 0 bcd value in 100 mv 2.7v 1ch 38h 0036h v cc logic supply maximum program/erase voltage bit 7 to 4 bcd value in volts bit 3 to 0 bcd value in 100 mv 3.6v 1dh 3ah 00b5h v pp [programming] supply minimum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 mv 11.5v 1eh 3ch 00c5h v pp [programming] supply maximum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 mv 12.5v 1fh 3eh 0004h typical timeout per single byte/word program = 2 n s 16s 20h 40h 0000h typical timeout for minimum size write buffer program = 2 n s na 21h 42h 000ah typical timeout per individual block erase = 2 n ms 1s 22h 44h 0000h typical timeout for full chip erase = 2 n ms na 23h 46h 0004h maximum timeout for byte/word program = 2 n times typical 256 s 24h 48h 0000h maximum timeout for write buffer program = 2 n times typical na 25h 4ah 0003h maximum timeout per individual block erase = 2 n times typical 8s 26h 4ch 0000h maximum timeout for chip erase = 2 n times typical na address data description value x16 x8 27h 4eh 0016h device size = 2 n in number of bytes 4 mbyte 28h 29h 50h 52h 0002h 0000h flash device interface code description x8, x16 async. 2ah 2bh 54h 56h 0000h 0000h maximum number of bytes in multi-byte program or page = 2 n na 2ch 58h 0002h number of erase block regions. it specifies the number of regions containing contiguous erase blocks of the same size. 2 2dh 2eh 5ah 5ch 0007h 0000h region 1 information number of identical size erase block = 0007h+1 8 2fh 30h 5eh 60h 0020h 0000h region 1 information block size in region 1 = 0020h * 256 byte 8kbyte 31h 32h 62h 64h 003eh 0000h region 2 information number of identical size erase block = 003eh+1 63 33h 34h 66h 68h 0000h 0001h region 2 information block size in region 2 = 0100h * 256 byte 64kbyte
41/49 m29dw324dt, m29dw324db table 27. primary algorithm-specific extended query table table 28. security code area address data description value x16 x8 40h 80h 0050h primary algorithm extended query table unique ascii string pri "p" 41h 82h 0052h "r" 42h 84h 0049h "i" 43h 86h 0031h major version number, ascii "1" 44h 88h 0030h minor version number, ascii "0" 45h 8ah 0000h address sensitive unlock (bits 1 to 0) 00 = required, 01= not required silicon revision number (bits 7 to 2) ye s 46h 8ch 0002h erase suspend 00 = not supported, 01 = read only, 02 = read and write 2 47h 8eh 0001h block protection 00 = not supported, x = number of blocks in per group 1 48h 90h 0001h temporary block unprotect 00 = not supported, 01 = supported ye s 49h 92h 0004h block protect /unprotect 04 = m29w400b 4 4ah 94h 0020h simultaneous operations, x = number of blocks in bank b 32 4bh 96h 0000h burst mode, 00 = not supported, 01 = supported no 4ch 98h 0000h page mode, 00 = not supported, 01 = 4 page word, 02 = 8 page word no 4dh 9ah 00b5h v pp supply minimum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 mv 11.5v 4eh 9ch 00c5h v pp supply maximum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 mv 12.5v 4fh 9eh 000xh top/bottom boot block flag 02h = bottom boot device, 03h = top boot device C address data description x16 x8 61h c3h, c2h xxxx 64 bit: unique device number 62h c5h, c4h xxxx 63h c7h, c6h xxxx 64h c9h, c8h xxxx
m29dw324dt, m29dw324db 42/49 appendix c. extended memory block the m29dw324d has an extra block, the extend- ed block, that can be accessed using a dedicated command. this extended block is 32 kwords in x16 mode and 64 kbytes in x8 mode. it is used as a security block (to provide a permanent security identifica- tion number) or to store additional information. the extended block is either factory locked or customer lockable, its status is indicated by bit dq7. this bit is permanently set to either 1 or 0 at the factory and cannot be changed. when set to 1, it indicates that the device is factory locked and the extended block is protected. when set to 0, it indicates that the device is customer lockable and the extended block is unprotected. bit dq7 being permanently locked to either 1 or 0 is another security feature which ensures that a customer lockable device cannot be used instead of a facto- ry locked one. bit dq7 is the most significant bit in the extended block verify code and a specific procedure must be followed to read it. see extended memory block verify code in tables 3 and 4, bus opera- tions, byte = v il and bus operations, byte = v ih , respectively, for details of how to read bit dq7. the extended block can only be accessed when the device is in extended block mode. for details of how the extended block mode is entered and exited, refer to the enter extended block com- mand and exit extended block command. para- graphs, and to tables 5 and 6, commands, 16-bit mode, byte = v ih and commands, 8-bit mode, byte = v il , respectively. factory locked extended block in devices where the extended block is factory locked, the security identification number is writ- ten to the extended block address space (see ta- ble 29, extended block address and data) in the factory. the dq7 bit is set to 1 and the extended block cannot be unprotected. customer lockable extended block a device where the extended block is customer lockable is delivered with the dq7 bit set to 0 and the extended block unprotected. it is up to the customer to program and protect the extended block but care must be taken because the protec- tion of the extended block is not reversible. there are two ways of protecting the extended block: n issue the enter extended block command to place the device in extended block mode, then use the in-system technique (refer to appendix d, in-system technique and to the corresponding flowcharts, figures 22 and 23, for a detailed explanation of the technique). n issue the enter extended block command to place the device in extended block mode, then use the programmer technique (refer to appendix d, programmer technique and to the corresponding flowcharts, figures 20 and 21, for a detailed explanation of the technique). once the extended block is programmed and pro- tected, the exit extended block command must be issued to exit the extended block mode and return the device to read mode. table 29. extended block address and data note: 1. see tables 21 and 22, top and bottom boot block addresses. device address (1) data x8 x16 factory locked customer lockable m29dw324dt 3f0000h-3f000fh 1f8000h-1f8007h security identification number determined by customer 3f0010h-3fffffh 1f8008h-1fffffh unavailable m29dw324db 000000h-00000fh 000000h-000007h security identification number determined by customer 000010h-00ffffh 000008h-007fffh unavailable
43/49 m29dw324dt, m29dw324db appendix d. block protection block protection can be used to prevent any oper- ation from modifying the data stored in the memo- ry. the blocks are protected in groups, refer to appendix a, tables 21 and 22 for details of the protection groups. once protected, program and erase operations within the protected group fail to change the data. there are three techniques that can be used to control block protection, these are the program- mer technique, the in-system technique and tem- porary unprotection. temporary unprotection is controlled by the reset/block temporary unpro- tection pin, rp ; this is described in the signal de- scriptions section. to protect the extended block issue the enter ex- tended block command and then use either the programmer or in-system technique. once pro- tected issue the exit extended block command to return to read mode. the extended block protec- tion is irreversible, once protected the protection cannot be undone. programmer technique the programmer technique uses high (v id ) volt- age levels on some of the bus pins. these cannot be achieved using a standard microprocessor bus, therefore the technique is recommended only for use in programming equipment. to protect a group of blocks follow the flowchart in figure 20, programmer equipment block protect flowchart. to unprotect the whole chip it is neces- sary to protect all of the groups first, then all groups can be unprotected at the same time. to unprotect the chip follow figure 21, programmer equipment chip unprotect flowchart. table 30, programmer technique bus operations, gives a summary of each operation. the timing on these flowcharts is critical. care should be taken to ensure that, where a pause is specified, it is followed as closely as possible. do not abort the procedure before reaching the end. chip unprotect can take several seconds and a user message should be provided to show that the operation is progressing. in-system technique the in-system technique requires a high voltage level on the reset/blocks temporary unprotect pin, rp . this can be achieved without violating the maximum ratings of the components on the micro- processor bus, therefore this technique is suitable for use after the memory has been fitted to the sys- tem. to protect a group of blocks follow the flowchart in figure 22, in-system block protect flowchart. to unprotect the whole chip it is necessary to protect all of the groups first, then all the groups can be unprotected at the same time. to unprotect the chip follow figure 23, in-system chip unprotect flowchart. the timing on these flowcharts is critical. care should be taken to ensure that, where a pause is specified, it is followed as closely as possible. do not allow the microprocessor to service interrupts that will upset the timing and do not abort the pro- cedure before reaching the end. chip unprotect can take several seconds and a user message should be provided to show that the operation is progressing. table 30. programmer technique bus operations, byte = v ih or v il note: 1. block protection groups are shown in appendix d, tables 21 and 22. operation e g w address inputs a0-a20 data inputs/outputs dq15aC1, dq14-dq0 block (group) protect (1) v il v id v il pulse a9 = v id , a12-a20 block address others = x x chip unprotect v id v id v il pulse a9 = v id , a12 = v ih , a15 = v ih others = x x block (group) protection verify v il v il v ih a0 = v il , a1 = v ih , a6 = v il , a9=v id , a12-a20 block address others = x pass = xx01h retry = xx00h block (group) unprotection verify v il v il v ih a0 = v il , a1 = v ih , a6 = v ih , a9 = v id , a12-a20 block address others = x retry = xx01h pass = xx00h
m29dw324dt, m29dw324db 44/49 figure 20. programmer equipment group protect flowchart note: block protection groups are shown in appendix d, tables 21 and 22. address = group address ai05574 g, a9 = v id , e = v il n = 0 wait 4s wait 100s w = v il w = v ih e, g = v ih , a0, a6 = v il , a1 = v ih a9 = v ih e, g = v ih ++n = 25 start fail pass yes no data = 01h yes no w = v ih e = v il wait 4s g = v il wait 60ns read data verify protect set-up end a9 = v ih e, g = v ih
45/49 m29dw324dt, m29dw324db figure 21. programmer equipment chip unprotect flowchart note: block protection groups are shown in appendix d, tables 21 and 22. protect all groups ai05575 a6, a12, a15 = v ih (1) e, g, a9 = v id data w = v ih e, g = v ih address = current group address a0 = v il , a1, a6 = v ih wait 10ms = 00h increment current group n = 0 current group = 0 wait 4s w = v il ++n = 1000 start yes yes no no last group yes no e = v il wait 4s g = v il wait 60ns read data fail pass verify unprotect set-up end a9 = v ih e, g = v ih a9 = v ih e, g = v ih
m29dw324dt, m29dw324db 46/49 figure 22. in-system equipment group protect flowchart note: block protection groups are shown in appendix d, tables 21 and 22. ai05576 write 60h address = group address a0 = v il , a1 = v ih , a6 = v il n = 0 wait 100s write 40h address = group address a0 = v il , a1 = v ih , a6 = v il rp = v ih ++n = 25 start fail pass yes no data = 01h yes no rp = v ih wait 4s verify protect set-up end read data address = group address a0 = v il , a1 = v ih , a6 = v il rp = v id issue read/reset command issue read/reset command write 60h address = group address a0 = v il , a1 = v ih , a6 = v il
47/49 m29dw324dt, m29dw324db figure 23. in-system equipment chip unprotect flowchart note: block protection groups are shown in appendix d, tables 21 and 22. ai05577 write 60h any address with a0 = v il , a1 = v ih , a6 = v ih n = 0 current group = 0 wait 10ms write 40h address = current group address a0 = v il , a1 = v ih , a6 = v ih rp = v ih ++n = 1000 start fail pass yes no data = 00h yes no rp = v ih wait 4s read data address = current group address a0 = v il , a1 = v ih , a6 = v ih rp = v id issue read/reset command issue read/reset command protect all groups increment current group last group yes no write 60h any address with a0 = v il , a1 = v ih , a6 = v ih verify unprotect set-up end
m29dw324dt, m29dw324db 48/49 revision history table 31. document revision history date version revision details 19-apr-2002 -01 document written 08-apr-2003 2.0 revision numbering modified: a minor revision will be indicated by incrementing the digit after the dot, and a major revision, by incrementing the digit before the dot (revision version 01 equals 1.0). revision history moved to end of document. when in extended block mode, the block at the boot block address can be used as otp. data toggle flow chart corrected. logic diagram corrected. tfbga48, 6x8mm, 0.8mm pitch package added. identification current i id removed from table 12, dc characteristics. erase suspend latency time and data retention parameters and notes added to table 7, program, erase times and program, erase endurance cycles. appendix c, extended memory block, added. auto select command sued to read the extended memory block. extended memory block verify code row added to tables 3 and 4, bus operations, byte = v il and bus operations, byte = v ih . bank address modified in auto select command. chip erase address modified in table 8, status register bits. v ss pin connection to ground clarified. note added to table 20, ordering information scheme. 07-may-2003 2.1 table 17, 48 lead plastic thin small outline, 12x20 mm, package mechanical data and figure 17, 48 lead plastic thin small outline, 12x20 mm, bottom view package outline corrected. 25-jun-2003 3.0 document promoted from preliminary data to full datasheet status. packing option added to table 20, ordering information scheme.
49/49 m29dw324dt, m29dw324db information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners ? 2003 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malt a - morocco - singapore - spain - sweden - switzerland - united kingdom - united states www.st.com

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